1. Field
Exemplary embodiments of the present invention relate to a semiconductor design technology, and more particularly, to a nonvolatile memory device including a power-on reset circuit, and a method of operating the same.
2. Description of the Related Art
Semiconductor memory devices are generally classified into volatile and nonvolatile memory devices. Volatile memory devices have an advantage in that read and write speeds are fast, but are disadvantaged in that stored content is not retained when external power is interrupted. Nonvolatile memory devices have an advantage in that stored content is retained even without external power. Accordingly, nonvolatile memory devices are used to store content that needs to be retained without a constant source of power.
A semiconductor memory device receives its power supply voltage from an internal or external power supply. When the power supply is suddenly interrupted (hereinafter, referred to as “sudden power-off; SPO”), a defect may occur, such as loss of data being programmed in the semiconductor memory device. Accordingly, in a sudden power-off, in order to stably retain data, a word line and a bit line are discharged. For such an operation, a discharging signal for discharging the word line and the bit line may be generated by detecting the power supply voltage that is supplied from the power supply.
A general semiconductor memory device includes a power-on reset (POR) circuit to prevent abnormal′ operations when power is supplied thereto. When the power supply voltage reaches a predetermined level after the power is supplied to the semiconductor memory device, the power-on reset circuit provides a reset signal for initializing a flip-flop, a latch, a counter, a register or the like. In general, when the power supply voltage reaches a predetermined level after power-on, the power-on reset circuit activates the reset signal. If the power supply voltage reaches a normal operation voltage, the power-on reset circuit deactivates the reset signal. In response to the activated reset signal, internal elements of the semiconductor memory device are reset to an initial state. Such a power-on reset circuit may also detect the level of the external power supply voltage and generate a power-on reset signal.
FIG. 1 is a circuit diagram illustrating a power-on reset signal generation unit and a discharging signal generation unit according to the prior art.
Referring to FIG. 1, a power-on reset signal generation unit 110 may include a PMOS transistor P1, a resistor R1, and a voltage level detection section 111.
The PMOS transistor P1 has a source coupled to an external power supply voltage (VCCE) terminal and a gate coupled to a ground voltage (VSS) terminal, and the resistor R1 is coupled between drain of the PMOS transistor P1 and the VSS terminal. When the PMOS transistor P1 is turned on, an external power supply voltage VCCE may be supplied to the power-on reset signal generation unit 110.
The voltage level detection section 111 may stably output an power-on reset signal POR when a voltage level of the external power supply voltage VCCE is equal to or greater than a preset level during power-on or is equal to or less than the preset level during power-down, after power-on.
A discharging signal generation unit 120 may include a resistor R2 and R3, a voltage level detection section 121 and an OR gate 122.
The resistor R2 is coupled between external power supply voltage VCCE terminal and the resistor R3, and the resistor R3 is coupled between the resistor R2 and the ground terminal VSS terminal.
The voltage level detection section 121 may stably output an internal discharging signal INT_DTVCC. The OR gate 122 may perform a logic operation on the internal discharging signal INT_DTVCC and the power-on reset signal POR, thereby outputting a discharging signal DTVCC.
The power-on reset signal generation unit 110 and the discharging signal generation unit 120 may generate a power-on reset signal POR and a discharging signal DTVCC, respectively, based on an external power supply voltage VCCE. In other words, the power-on reset signal generation unit 110 and the discharging signal generation unit 120 may generate the discharging signal DTVCC and the power-on reset signal POR to be used in a sudden power-off by detecting the voltage level of the external power supply voltage VCCE. When the discharging signal DTVCC and the power-on reset signal POR are generated, the discharging signal DTVCC has to be generated earlier than the power-on reset signal POR. When powering-off (reducing the voltage level) of the external power supply voltage VCCE, the detection level of the discharging signal DTVCC may be set to be higher than the detection level of the power-on reset signal POR. However, a PMOS transistor P1 used in the power-on reset signal generation unit 110 is very sensitive to changes in skew, such as temperature or resistance. Due to the change in skew, a reversal phenomenon in which the power-on reset signal POR is generated earlier than the discharging signal DTVCC may occur. This concern is illustrated in FIG. 2.
FIG. 2 is a timing diagram illustrating a reversal phenomenon of the power-on reset signal according to the prior art.
Referring to FIG. 1 and FIG. 2, in the sudden power-off in which the supply of the external power supply voltage VCCE is suddenly interrupted, since the discharging signal DTVCC has to be generated earlier than the power-on reset signal POR, the detection level of the discharging signal DTVCC is higher than the detection level of the power-on reset signal POR. However, depending on the change in skew of the PMOS transistor P1 provided in the power-on reset signal generation unit 110, a reversal phenomenon in which the power-on reset signal POR is generated earlier than the discharging signal DTVCC may occur. When the reversal phenomenon occurs, since a word line is initialized by the power-on reset signal POR before being discharged, it is difficult to stably retain data stored in a cell.
Due to such concerns, the detection level of the discharging signal DTVCC may be set to be higher than the detection level of the power-on reset signal POR. The detection level of the discharging signal DTVCC may be set from 2 V to 1.8 V and the detection level of the power-on reset signal POR may be set from 1.7 V to 1.4 V. For example, when the detection level of the discharging signal DTVCC is set to 2 V, the external power supply voltage VCCE may suddenly drop due to excessive current consumption by an internal operation. In such case, it may be detected as a sudden power-off and the discharging signal DTVCC may be activated. Therefore, as illustrated in FIG. 2, a low VCCE margin has to be kept in order to cope with the drop phenomenon.
In brief, when the difference between the detection levels of the discharging signal DTVCC and the power-on reset signal POR is small, an abnormal operation may occur due to the reversal phenomenon caused by a change in skew of the power-on reset signal POR. Furthermore, when the detection level of the discharging signal DTVCC is set high, the discharging signal DTVCC may be activated by the drop phenomenon, resulting in the occurrence of an abnormal operation.